The present invention relates to a method for fabricating an integrated circuit and the structure formed therefrom, and particularly to the method for fabricating a trench device and a planar device simultaneously and to the structure obtained therefrom.
The power metal oxide semiconductor field effect transistor (MOSFET/MOS) has a high input impedance, and thus the power MOS is easily damaged by an electrostatic discharge (ESD) protection pulse. Moreover, the MOS with lower threshold voltage (Vt) is desirable so that the thickness of its gate oxide layer should be maintained thin. Under such a requirement, once 15–20 voltages are applied to the MOS, the gate oxide thereof would be easily damaged and the problem of an electric leakage may occur. Therefore, it is necessary to employ an electrostatic discharge protection circuit in the application of a power MOS.
According to the conventional technique for fabricating an integrated circuit, a power MOS is fabricated first, and then an electrostatic discharge protection circuit is formed. The N type MOS is one example. In the conventional trench double-diffused MOS (trench-DMOS) manufacturing process, a semiconductor material of the epitaxial silicon layer has trenches, and firstly an oxide layer is formed on the surface of the semiconductor material.
After the oxide layer is formed, a doped polysilicon layer is filled into the trenches and the gate of the power MOS would be formed by subsequently etching the doped polysilicon layer exposed outside of the trenches. When the gate of the power MOS is formed, a second polysilicon layer is deposited on the surface of the oxide layer and then some P type dopants are fully implanted into this polysilicon layer. Next, a photoresist is employed to protect a part of this polysilicon layer from a second polysilicon etching so as to form the polysilicon layer for the electrostatic discharge protection circuit.
FIG. 1 is a schematic view showing a conventional trench double-diffused MOS with an ESD protection circuit. The epitaxial layer epi is used for the semiconductor material and has the trenches 14. On the surface of the semiconductor material is the oxide layer 12. The oxide layer 12 can be used as the gate oxide layer of the trench MOS 15 and the dielectric layer of the ESD protection circuit 17 simultaneously. On the oxide layer 12, the trench MOS 15 and the ESD protection circuit 17 are formed thereon. The gate 11 of the trench MOS 15 and the polysilicon layer 13 of the ESD protection circuit 17 are formed from the first and the second etching respectively. The above two etching and the washing in the acid tanks thereafter would erode the corner gate oxide layer 121, and would cause the electric leakage on the gate oxide layer. Furthermore, in order to cope with the electric demand of fabricating a thin gate oxide layer, the problem of electric leakage would become serious.
In the conventional technique, a power MOS is fabricated first, and then an electrostatic discharge (ESD) protection circuit is formed. Under such a manufacturing process, two polysilicon layer depositions and two polysilicon layer etchings are used so that the gate oxide layer is easily eroded and thus the problem of electric leakage would occur.
Therefore, how to simplify the manufacturing process and how to prevent the gate oxide layer from an erosion have become the major problems waiting to be solved in the industry. In order to overcome the drawbacks in the prior art, a method and the structure for fabricating an integrated circuit are provided. In the particular invention, the problem of electric leakage is solved and it has the advantages of reducing the relevant costs and increasing the yields.